1. Field of the Invention
The present invention relates to a receiver that automatically determines the data rate.
2. Description of Prior Art
To transmit digital data over a link, such as a twisted-pair copper cable, a transceiver is required. A transceiver contains a local transmitter which broadcasts the digital information over the link and a local receiver which receives information on the link sent by a remote transmitter. The receiver re-creates the information sent by the remote transmitter by compensating for the losses induced by the link on the transmitted signal. Proper operation requires that both transmitter and receiver are configured to transmit and receive information according to a prescribed line code and data rate. For example, in Ethernet applications common transceivers can support 10 Mb/s (Manchester code) or 100 Mb/s (MLT3 code). In multi-rate transceiver circuits, it is possible to support more than one data rate (line code). For example, a xe2x80x9c10/100xe2x80x9d Ethernet transceiver must accommodate both 10 Mb/s and 100 Mb/s data traffic. Hence, a transceiver must have the capability to decide which mode of operation it is to support for a given link. The decision process is termed xe2x80x9cautonegotiationxe2x80x9d. During autonegotiation, the two transceivers on opposite ends of the link communicate by transmitting information encapsulated within a periodic burst of closely spaced pulses. These pulses are termed xe2x80x9cfast link pulsesxe2x80x9d (FLPs), and are defined by IEEE standard 802.3. Based on the information conveyed by the pulses (frequency, number), both receivers can decipher what line code capabilities the remote transceiver can support. Once this is known, both transceivers are placed in a line code mode that both can support. If they can support more than one line code, the common capability that is chosen depends on an established priority.
Since autonegotiation is a relatively new feature, native transceivers do not support this protocol. Thus another mechanism is required to determine the capability of the link partners. This mechanism involves a signal detect circuit that monitors the incoming signals to decide which line code is being transmitted. Typically if a link is not established, a transceiver is in the idle state, in which case it sends certain distinct patterns. These patterns can be detected by the receiver to decide the remote transmitter line code. Notice that the more line codes one must support, the harder it is to establish which line code is being received based on the data being received. Hence the need for the autonegotiation protocol. The combination of the signal detect mechanism and the autonegotiation mechanism is termed xe2x80x9cparallel detectionxe2x80x9d.
When a transceiver is powered up it must constantly remain in this parallel detection mode (i.e. xe2x80x9clisten to the wirexe2x80x9d). In many situations this state can be lengthy, thus it is necessary to keep power dissipation low during this state as the transceiver is not performing any data transfers but idle. Typical solutions for parallel detection circuitry in 10/100 transceivers is to turn on both the 10 Mb/s receiver and the 100 Mb/s receiver and based on their outputs decide on a common capability between the link partners. Unfortunately, this solution requires significant power. In fact, this idle state dissipates more power than the operating mode, since once a common capability is established, only one receiver is powered up (10 or a 100, not both).
FIG. 1 shows an embodiment of a typical 10/100 receive architecture to achieve parallel detection, which is usually implemented on a single integrated circuit (IC) in present-day designs. As used herein, a 10 Base-T transceiver is also referred to as xe2x80x9c10BTxe2x80x9d, a 100 Base-TX transceiver as xe2x80x9c100TXxe2x80x9d, and a 100 Base-T4 transceiver as xe2x80x9c100BT4xe2x80x9d. During autonegotiation both receivers 101 and 102 are active, and supply their output signals to the parallel detect block 103. The output of the 10BT (10 Mb/s) receiver 101 goes to the FLP block 104, which monitors the received signal. If proper pulse bursts are detected with the correct frequency and number, the FLP block will determine which of links 100TX or 10BT to establish by asserting or de-asserting the FLP signal, which causes the control block (107) to assert either the 100TX or the 10BT signal, respectively. An asserted 100TX signal (e.g., high voltage) causes the OR gate 108 to place a xe2x80x9cdisablexe2x80x9d signal on the disable input of the 10BT receiver 101, thereby allowing only the 100TX receiver 102 to remain active. Alternatively, an asserted 10BT signal causes the OR gate 109 to place a xe2x80x9cdisablexe2x80x9d signal on the disable input of the 100TX receiver 102, thereby allowing only the 10BT receiver 101 to remain active. If the received signal does not contain proper FLP bursts, a FAIL condition will be reported by the control block 107. In this case, link information will be obtained from the signal detect blocks; SD (105) for the 100 Mb/s mode and NLP (106) for the 10 Mb/s mode.
For example, a typical prior-art solution for implementing the SD block employs a peak detector on the post-equalized receiver output. If the post-equalized signal exceeds a certain threshold level for a given time period, the SD output is asserted, indicating a 100 Mb/s link. De-assertion of the SD output occurs if the peak level of the post-equalized output falls below the threshold level in a given time period. Another prior-art technique asserts the SD output when the 100M/bs receiver phase locked-loop (used for timing recovery) acquires lock. Still another prior-art technique makes use of the adaptation output behavior to assert the SD output. In any of these cases, the asserted SD output causes the OR gate 108 to place a disable signal on the disable input of the 10BT receiver section 101. To check for 10 Mb/s activity, a typical prior-art technique is to check for the idle pattern that this line code provides. These idle patterns are termed xe2x80x9cnormal link pulsesxe2x80x9d (NLPs), and are essentially pulses with a duration of 100 ns and with a predictable period, as defined by ISO/IEC 8802-3 and ANSI/IEEE 802.3. If these pulses are detected in a given time period the NLP block 106 asserts the NLP signal. This assertion causes the OR gate 109 to place a disable signal on the disable input of the 100TX receiver section 102. In the foregoing manner, either the 100TX or 10BT signal indicators will be active so that the transceiver can decipher the capability of its link partner if the autonegotiation protocol fails. Note that an xe2x80x9cotherxe2x80x9d output may be provided from block 107, to indicate the presence of another signal protocol (e.g., 100BT4). It is evident that the prior-art techniques requires both the 10 Mb/s and the 100 Mb/s receivers to be active during this autonegotiation phase, which can be lengthy as discussed above; thus, power dissipation in this state can be quite high.
Referring to FIG. 2, a typical implementation of an analog 100TX receiver shows various components that tend to consume significant amounts of power when activated. The baseline wander block (20) provides for correction of DC offset voltages due to asymmetrical data streams, while the automatic gain control block (21) compensates for amplitude differences. These amplitude differences may be due to the insertion loss and variations in the transmitter output, for example. The equalizer (22) corrects for varying cable lengths and differences in phase delays, and the comparators (23) provide for detection of the data, while the phase-locked loop (24) provides for recovery of the clock from the received data. Referring to FIG. 3, a typical implementation of a digital receiver includes an automatic gain control (30), an equalizer (31), an analog-to-digital converter (32) providing digital signal to a digital signal processor (33) over a bus (34). While various receiver designs differ in which of these blocks to include, they typically include most of them.
We have invented a signal rate detection technique for use in a multi-data rate receiver that uses comparators to obtain information on the incoming data for enabling the appropriate receiver section. A first comparator detects a relatively low data rate signal, and a second comparator detects a relatively high data rate signal. Logic circuitry activates a first receiver section when the first comparator detects the relatively low data rate signal, and activates the second receiver section when the second comparator detects the relatively high data rate signal.